3V LVDS QUAD CMOS DIFFERENTIAL LINE DRIVER

This specification applies to devices over the recommended operating temperature and voltage ranges, and across process distribution. Other configurations are possible such as a multireceiver configuration, but the effects of a mid-stream connector s , cable stub s , and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account. AC or unterminated configurations are not allowed. This component has a RoHS exemption for either 1 lead-based flip-chip solder bumps used between the die and package, or 2 lead-based die adhesive used between the die and leadframe. Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode rejection of the receivers. Channel 2 Noninverting Output Current Driver.

Uploader: Mogami
Date Added: 20 January 2005
File Size: 26.48 Mb
Operating Systems: Windows NT/2000/XP/2003/2003/7/8/10 MacOS 10/X
Downloads: 34179
Price: Free* [*Free Regsitration Required]

The differential voltage is detected by the receiver and converted back into a single-ended logic signal.

DS90LV031AQML 3V LVDS Quad CMOS Differential Line Driver

The receiver output will be High for all failsafe conditions. Only one output should be shorted at a time, do not exceed maximum junction temperature specification. LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 6. Production processing does not necessarily include testing of all parameters.

The received voltage is centered around the receiver offset of 1. Carefully review dimensions to match differential impedance and provide isolation for the differential lines. The internal lins will guarantee a high, stable output state.

DS90LV031 3V LVDS Quad CMOS Differential Line Driver

Improper probing will give deceiving results. The DS90LV differential line driver is a balanced current source design.

  C-MEDIA CMI9738 PCI DRIVER

Point-to-Point Application Applications Information The receiver also supports a failsafe feature which provides a stable known state high output voltage for any of the following conditions: National Semiconductor Corporation Americas Tel: Output cmox circuit current IOS is specified as magnitude only, minus sign indicates direction only.

Channel 2 Inverting Output Current Driver.

Channel to Channel Skew is defined as the difference between the propagation differenhial of the channel and the other channels in the same chip with any event on the inputs. A termination resistor of X should be selected to match the media, and is located as close to the receiver input pins as possible. External lower value pull up and pull down resistors for a stronger bias may be used to boost fail-safe in the presence of higher noise levels.

The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Separable differential equations Work your. All other trademarks are the property of their respective owners.

Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. Other inputs are set to GND. The current mode driver provides substantial benefits over voltage mode drivers, such as an RS driver. The quar high and active low enable inputs deactivate all the current drivers when the drivers are in the disabled state.

DS90LV 3V LVDS Quad CMOS Differential Line Receiver

Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. These inputs control all four drivers and turn off the current outputs in the disabled state to reduce the quiescent power consumption to typically 10 mW.

  M1530 MFP SCAN DRIVER

If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0V differential input voltage, the receiver output will remain in a HIGH state. Specifications subject to change without notice. It is only supported with inputs shorted and no external common-mode voltage applied.

3 V, LVDS, Quad, CMOS Differential Line Driver ADN

Other configurations are possible such as a multi-receiver configuration, but lihe effects of ovds mid-stream connector scable stub sand other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account. Current is switched through the load in one direction to produce a logic state and in the other direction to produce the other logic state.

Match electrical lengths between traces to reduce skew. This can be prevented with minimal impact diffrrential the DS90LV AC performance by installing a kX pull down resistor on the minus receiver input pin to ground. LVDS will not work without resistor termination.

Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.